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RT6010 ? ds6010-00 march 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. dual channel high efficiency and high accuracy average current control led backlight buck controller general description the RT6010 is a dual channel high accuracy average current control led backlight buck controller for 2 led strings w/ o led binning. dual mosfet drivers are specifically designed to drive two power n-mosfets in an asynchronous buck converter topology. the controller provides variable led current control by adjusting the cs resistor value for digital and linear dimming. the controller operates with t1/t2 average current control (t 2 c) topology to provide high accuracy 3%. the controller also provides high efficiency (higher than 95%) under proper setting without led binning. the controller provides v in from 8v to 450v. it is preferred to operate the controller under a current ripple of < 30% average current and about 85% duty to optimize the performance. the RT6010 can be easily connected in series by master/ slave synchronization for multiple channel, even for more than 6-ch. the controller provides spd (smart phase shift dimming) that is easily implemented to synchronize master and slave ics. the controller provides both analog and pwm dimming. the RT6010 automatically detects led bar open, led bar short to v in , and led bar short to gnd to prevent vout from over/under voltage damages. the controller also outputs fault signal with programmable delay to previous power stage, such as acdc controller. features z z z z z fast average current control t 2 c (t1/t2 average current control) z z z z z dual mosfet drives for asynchronous buck topology z z z z z provide high efficiency > 95% and high accuracy 3% channel to channel variation z z z z z provide led w/o binning z z z z z programmable pwm constant off time z z z z z support both pwm and analog dimming z z z z z pwm dimming duty down to 1% z z z z z ovp for bar short with v in z z z z z uvp for bar open/short to gnd with programmable fault delay z z z z z support spd (smart phase shift dimming) for multiple channel dimming solution z z z z z v in por detection with en pin to prevent malfunction z z z z z sop-16 package z z z z z rohs compliant and halogen free applications z lcd tv, mnt display backlight z dc/dc or acdc led driver application z general purpose constant current source z led signage and display z architectural and decorative led lighting z led street lighting pin configurations (top view) sop-16 vss pwm_out en rt_out cs2 gate2 gate1 vcc dim/pwm_in rt d_osc f_delay fault nc cs1 dps 6 7 8 4 5 2 3 16 13 15 14 12 9 11 10 package type s :sop-16 RT6010 lead plating system g : green (halogen free and pb free)
RT6010 2 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 2. synchronization for multiple channel_digital figure 1 marking information RT6010 gsymdnn RT6010gs : product number ymdnn : date code vcc epwm/ipwm v cc high : disable spd function low : support spd en dim/pwm_in dps f_delay d_osc RT6010 vss nc rt rt_out pwm_out gate1 cs1 gate2 cs2 slave ic slave ic 0.22f 4.7mh 4.7mh 0.22f v in 1 13 2 6 8 5 4 16 7 3 14 15 12 11 9 10 chip enable 12v fault c d_osc c f_delay c vcc r cs2 q2 l2 d2 d1 l1 r cs1 c out1 c out2 q1 c in 10f 10nf 10nf r rt 180k 5 5 120f/450v vcc en dim/pwm_in dps f_delay d_osc RT6010 (stage_1) vss rt rt_out pwm_out gate1 cs1 gate2 cs2 12v fault 5v en vcc en dim/pwm_in dps f_delay d_osc RT6010 (stage_2) vss rt rt_out pwm_out gate1 cs1 gate2 cs2 4.7mh 4.7mh fault 5v fault stage_3 dim/pwm_in stage_3 rt v in high : disable spd function low : support spd 0.22f 4.7mh 4.7mh 0.22f q2 d2 d1 q1 10f 10nf 5 5 120f/450v 50k 180k 10nf 0.22f 0.22f q4 d4 d3 q3 5 5
RT6010 3 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 vcc power supply for pwm controller. 2 dim/pwm_in dimming pwm pulse input or analog voltage input. 3 rt constant off time setting by connecting proper resistor to vss. 4 d_osc for analog dimming, d_osc should be connected to a capacitor to generate dimming triangle oscillator that is compared with dim/pwm_in dc voltage level to generate pwm dimming pulse. for digital dimming, d_osc should be connected to vss. 5 f_delay define fault pin output delay by connecting to a proper capacitor to prevent false trigger for uvp and otp. 6 fa u lt open drain output fault including uvp, ovp, and otp (active low). 7 nc no internal connection. 8 dps smart phase shift dimming disable pin. pull dps high to disable function. 9 cs1 channel 1 current sense input. 10 gate1 channel 1 current gate driver output. 11 gate2 channel 2 current gate driver output. 12 cs2 channel 2 current sense input. 13 en chip enable (active high). enable pwm system, prefer connect to v in resistive voltage divider to guarantee v in power ready to prevent from pwm malfunction. 14 rt_out output for the next RT6010 rt. 15 pwm_out spd (smart phase shift dimming) output for slave to synchronize dimming phase shift. 16 vss ground. figure 3. synchronization for multiple channel_analog vcc en dim/pwm_in dps f_delay d_osc RT6010 (stage_1) vss rt rt_out pwm_out gate1 cs1 gate2 cs2 v in 12v fault 5v en vcc en dim/pwm_in dps f_delay d_osc RT6010 (stage_2) vss rt rt_out pwm_out gate1 cs1 gate2 cs2 4.7mh 4.7mh fault 5v fault stage_3 dim/pwm_in stage_3 rt high : disable spd function low : support spd 0.22f 4.7mh 4.7mh 0.22f q2 d2 d1 q1 10f 10nf 5 5 120f/450v 50k 180k 10nf 0.22f 0.22f q4 d4 d3 q3 5 5 22nf 1k 10nf
RT6010 4 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram gate1 gate2 average control logic average control logic + - dimming control protection otp bar open bar short to vin bar short to gnd osc + - cs1, cs2 pwm_out rt_out vcc vss off_time control 10a 1v 2v enable en_pwm1 en_pwm2 cs1 en cs2 dim/pwm_in d_osc dps rt f_delay fault
RT6010 5 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) z control input voltage, v cc ------------------------------------------------------------------------------------------------ 12v 10 % z supply input voltage, v in -------------------------------------------------------------------------------------------------- 8v to 450v z junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage, v cc -------------------------------------------------------------------------------------------------------- ? 0.3v to 15v z d_osc, pwm_out -------------------------------------------------------------------------------------------------------- ? 0.3v to 7v z others pins ------------------------------------------------------------------------------------------------------------------- ? 0.3v to 15v z power dissipation, p d @ t a = 25 c sop-16 ---------------------------------------------------------------------------------------------------------------------- -- 1.176w z package thermal resistance (note 2) sop-16, ja ------------------------------------------------------------------------------------------------------------------- 85 c/w z lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------------- 150 c z storage temperature range ---------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------------- 200v parameter symbol test conditions min typ max unit supply input supply current i vcc v boot = 12v, v dim/pwm_in = 5v, v csx = 0.3v -- 4 -- ma shutdown current i shd n without hv ldo ? lower shut down current 1ma -- -- 1 ma uvlo threshold v uvlo 7 8 9 v uvlo hysteresis v uvlo -- 1 -- v logic-high v ih 2 -- -- dim/pwn_in threshold voltage logic-low v il -- -- 0.6 v logic-high v oh 2.4 -- -- pwm_out threshold voltage logic-low v ol -- -- 0.4 v en threshold -- 2 -- v en hysteresis -- 0.2 -- v pwm controller cs v ref -- 500 -- mv on-time t on recommend 2 8 20 s constant off-time t off set up by rt(set 66.6k ) 0.8 1 1.2 s duty recommend customer application duty 40 85 90 %
RT6010 6 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit pwm frequency defined by t off 50 100 300 khz channel-to-channel accuracy -- 1.6 -- % protection ovp led string short -- 1 -- v uvp led string no connection -- 100 -- mv f_delay detect voltage bar open, bar short to gnd, bar short to v in & otp 0.9 1 1.1 v f_delay current source -- 10 -- a fault open drain ability -- -- 100 uvp/ovp blanking time -- 500 -- ns uvp delay time to gate off -- 250 -- ns otp -- 160 -- c otp hysteresis -- 20 -- c dimming pwm dimming frequency 100 -- 600 hz min dimming pulse 5 -- -- s forced dimming delay time (high) force dimming to h when dim/pwm_in goes h for too long -- 25 -- ms high-level v ih when operating at analog dimming, we recommend dim below 2.4v -- 2.5 -- d_osc input low-level v il when operating at analog dimming, we recommend dim above 1.1v -- 1 -- v d_osc sourcing current -- 10 -- a d_osc sinking current -- 10 -- a driver capability gate driver source v cc = 12v, v gatex = 9v -- 80 -- ma gate driver sink v cc = 12v, v gatex = 3v -- 200 -- ma
RT6010 7 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics led current vs. analog dimming voltage 0 20 40 60 80 100 120 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 analog dimming voltage (v) led current (ma) i led1 v in = 120v, v out1 = v out2 = 90v, 56leds i led2 efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 input voltage (v) efficiency (%) v out1 = v out2 = 90v, 56leds, i led1 = i led2 = 100ma, r rt = 180k led current vs. output voltage 90 92 94 96 98 100 102 104 106 108 110 60 65 70 75 80 85 90 95 100 output voltage (v) led current (ma) i led1 i led2 v in = 120v, i led1 = i led2 = 100ma, r rt = 180k led current vs. input voltage 90 92 94 96 98 100 102 104 106 108 110 110 120 130 140 150 160 170 180 190 200 input voltage (v) led current (ma) i led1 v out1 = v out2 = 90v, 56leds, i led1 = i led2 = 100ma, r rt = 180k i led2 led current vs. temperature 90 94 98 102 106 110 -50 -25 0 25 50 75 100 125 temperature (c) led current (ma) i led1 v in = 120v, v out1 = v out2 = 90v, 56leds, i led1 = i led2 = 100ma, r rt = 180k i led2 led current vs. pwm duty cycle 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100 duty cycle (%) led current (ma) i led1 v in = 120v, v out1 = v out2 = 90v, 56leds, r rt = 180k , c out = 0.22 f i led2
RT6010 8 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pwm dimming response time (50 s/div) i led1 (100ma/div) pwm (5v/div) i led2 (100ma/div) c out = 0.22 f, i led1 = i led2 = 100ma v in = 120v, v out1 = 100v, 31leds v out2 = 80v, 25leds, pwm = 300hz time (1ms/div) non-spd function i led1 (100ma/div) i in (100ma/div) v in_ac (500mv/div) i led2 (100ma/div) pwm = 300hz, pwm duty = 30% v in = 120v, v out1 = v out2 = 90v, 56leds spd function time (1ms/div) i led1 (100ma/div) i in (100ma/div) v in_ac (500mv/div) i led2 (100ma/div) pwm = 300hz, pwm duty = 30% v in = 120v, v out1 = v out2 = 90v, 56leds pwm dimming response time (50 s/div) v in = 120v, v out1 = v out2 = 90v, 56leds, pwm = 300hz, c out = 0.22 f, i led1 = i led2 = 100ma i led1 (100ma/div) pwm (5v/div) i led2 (100ma/div) led current vs. pwm duty cycle 0 10 20 30 40 50 60 70 80 90 100 0 20406080100 duty cycle (%) led current (ma) i led1 i led2 v in = 120v, v out1 = 100v 31leds, v out2 = 80v, 25leds pwm = 300hz, c out = 0.22 f
RT6010 9 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT6010 is a du al channel, high accuracy current control led backlight buck controller. the controller is capable of providing efficiency higher than 95% for led backlight use. current setting current flow through the inductor during charging period is detected by a sensing resistor, r cs . the RT6010 provides average current mode by dynamically adjusting v ref . the led average current can be set as : out cs 500mv i = r constant off-time setting the RT6010 is a constant off-time control ic. the off-time can be set via the external rt pin resistance, r rt . the switching frequency is usually designed to be between 50khz to 300khz, so the constant off-time must also meet the following condition : in led off in off rt v - v 50k 300k t x v t = 15p x r ? where t off is the constant off-time smart phase shift dimming the RT6010 provides dimming function selection via the dps pin. if the pin is connected to vcc, the two dimming signals will be in sync for those two channels. on the other hand, if the pin is connected to gnd, the two dimming signals will be separated. see figure below. figure 4 . smart phase shift dimming via the dps pin dps = vcc dim/pwm_in gate1 gate2 dps = gnd dim/pwm_in gate1 gate2 analog dimming frequency setting the RT6010 not only provides digital dimming, but also analog dimming as well. the analog dimming frequency is set via the d_osc pin. note that the minimum dimming duty is 6.667%. the dimming frequency is set according to the following equation : pwm d_osc f = 10 a / (c 3v) where c d_osc is the capacitor connected from the d_osc pin to gnd. protection functions the RT6010 provides various protection features to prevent damage to the ic during abnormal situations. the features include over voltage protection, under voltage protection, and over temperature protection. the protection flow chart is shown below. flt blanking delay an flt blanking delay function is ava ilable for setting the fault delay time to prevent false triggers for uvp and otp. the delay time is set via the external capacitor connected from the f_delay pin to ground. the blanking delay time can be set according to below equation : f_delay 1v t = c x 10 a where c f_delay is the capacitor connected from the f_delay pin to gnd. after v f_delay > 1v, a fault signal will be sent to the fault pin. over voltage protection the RT6010 provides over voltage protection (ovp) when the led cathode becomes shorted to vin. the ovp threshold voltage of the csx pin is approximately 1v. if ovp is triggered during gate-on period, the controller will turn off the mosfet for 400 s. if ovp occurs consecutively for more than 14 times, the RT6010 will send a fault signal to the fault . under voltage protection for situations where the led cathode becomes open or shorted to gnd, the RT6010 provides under voltage protection (uvp). the threshold voltage of uvp is approximately 0.1v. if uvp occurs during gate-on period, the RT6010 will send a fault signal to the fault pin after the fault delay time.
RT6010 10 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. led off out v l > x t 0.3 x i where v led is the led series voltage drop, t off is the pwm off-time, and i out is the led average current. figure 5. protection flow chart for the RT6010 over temperature protection to prevent excessive power dissipation from damaging the device, the RT6010 includes an over temperature protection feature. when the temperature rises above otp temperature, a fault signal will be sent to disable the channel after the fault delay time. after the die temperature falls below otp hysteresis temperature, the channel will be enabled again. inductor selection the inductor current ripple is usually designed below 30% of its average current. hence, the recommended inductor value can be calculated as : gate = low ovp times = 0 f_delay pull low fault = high v in , v cc power up start normal gate switch keep ovp times f_delay pull low fault = high after gate = high for 750ns detect cs pin > 1v gate switch keep ovp times f_delay pull low fault = low ovp times > 14 tj > 160c gate = low ovp times + 1 f_delay pull low fault = high after gate = hi gh for 750ns detect cs pin < 0.1v en = high &vcc > uvlo voltage f_delay voltage > 1v tj < 140c gate = low keep ovp times 10a current charge c f_delay fault = low gate = low keep ovp times 10a current charge c f_delay fault = high gate switch keep ovp times 10a current charge c f_delay fault = high f_delay voltage > 1v after gate = high for 750ns detect cs pin > 0.1v gate = low timing > 400s en = low / vcc < uvlo voltage gate switch keep ovp times f_delay pull low fault = low after gate = low detect cs pin > 0.5v continue 1.4s v cc < 3v gate switch keep ovp times 10a current charge c f_delay fault = low v cc > 5v gate switch keep ovp times f_delay pull low fault = low tj < 140c mosfet selection for operating at high input or output voltages, the power n-mosfet switch is typically chosen according to the drain voltage, v ds , rating and low gate charge. consideration of switch on-resistance, r ds(on) , is usually secondary because switching losses dominate power loss. the gate driving voltage follows the v cc voltage range, which is 12v for normal operation. the n-mosfet must meet this specification. capacitor selection selecting a suitable capacitor can reduce led current ripple and increase led life-time. moreover, if the capacitor has good current sense linearity, it will also ensure that the current matching is accurate. note that having too large of a capacitance will cause the led current to respond slowly. the typical value of the capacitor is 0.22 f.
RT6010 11 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vcc 12v v cc en v in r en1 910k r en2 30k figure 6. circuit for proper power on via en pin figure 7. (a) proper start up with r en1 , r en2 resistors v in en v cc start detect uvp v cc v in en start detect uvp figure 7. (b) uvp malfunction without r en1 , r en2 resistors v cc v in en start detect uvp if v cc and v en power on before v in powers on, uvp fault will be triggered. figure 7. timing diagram for power on sequence diode selection ultra-fast diodes are chosen for their low forward voltage drop and fast switching speed. when selecting ultra-fast diodes, im portant parameters such as power dissipation, reverse voltage rating, and pulsating peak current should all be taken into consideration. a suitable ultra-fast diode's reverse voltage rating must be greater than the input voltage and its average current rating must exceed the led average current. power on for power on sequence, it is recommended to connect en to a resistive voltage divider placed between v in and gnd to prevent uvp malfunction, as shown below. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-16 package, the thermal resistance, ja , is 85 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (85 c/w) = 1.176w for sop-16 package
RT6010 12 ds6010-00 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations pcb layout plays an important role for the RT6010. careful layout can decrease switching noise for stable operation and improve performance. for best performance of the RT6010, the following layout guidelines should be strictly followed. ` current sense feedback resistors, d_osc capacitor, f_delay capacitor, rt resistor and capacitors for vin and vcc should be placed as close to the controller as possible. ` keep the power loops as short as possible to prevent voltage spikes caused by current transition from one device to another at high speed as a result of parasitic components on the circuit board. therefore, all current switching loops should be kept as short as possible with wide traces to minimize the parasitic components. ` minimize the trace length between the mosfet and the controller. since the drivers are integrated in the controller, the driving path should be short and wide to reduce the parasitic inductance and resistance. ` the cs1 and cs2 current sense feedback trace should be kept away from the switching node. keep the feedback trace close to the cs1 and cs2 pins. allow large area for vin inductor trace, fet trace, r cs1 and r cs2 trace, and gnd pad. figure 8. derating curve of maximum power dissipation 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb figure 9. pcb layout guide vss pwm_out en rt_out cs2 gate2 gate1 vcc dim/pwm_in rt d_osc f_delay fault nc cs1 dps 6 7 8 4 5 2 3 16 13 15 14 12 9 11 10 vcc gnd + gnd gnd l2 r cs2 q1 c out2 v in c out1 l1 r cs1 q2 c in gnd current sense feedback resistors, d_osc capacitor, f_delay capacitor, rt resistor and capacitors for vin and vcc should be placed as close to the controller as possible. place the power components as close to the ic as possible. the current sense node must be near the cs pin. the gnd traces should be wide and short. the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT6010 13 ds6010-00 march 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension f b c i h d a j m dimensions in millimeters dimensions in inches symbol min max min max a 9.804 10.008 0.386 0.394 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.254 0.007 0.010 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 16 ? lead sop plastic package

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